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? semiconductor components industries, llc, 2013 february, 2013 ? rev. 14 1 publication order number: NOII4SM6600A/d NOII4SM6600A 6.6 megapixel cmos image sensor features ? 2210 (h) x 3002 (v) active pixels ? 3.5 m x 3.5 m square pixels ? 1 inch optical format ? monochrome output ? frame rate: ? 5 fps for active window of 2210 x 3002 ? 89 fps for active window of 640 x 480 ? high dynamic range modes: double slope, non destructive read out (ndr) ? electronic rolling shutter ? master clock: 40 mhz ? single 2.5 v supply ? 3.3 v supply for extended dynamic range ? ? 30 c to +65 c operational temperature range ? 68-pin lcc package ? power dissipation: 225 mw ? these devices are pb ? free and are rohs compliant applications ? machine vision ? biometry ? document scanning description the ibis4-6600 is a solid-state cmos image sensor that integrates complete analog image acquisition, and a digitizer and digital signal processing system on a single chip. this image sensor has a resolution of 6.6 mpixel with 2210 x 3002 active pixels. the image size is fully programmable for user-defined windows. the pixels are on a 3.5 m pitch. the user programmable row and column start and stop positions enable windowing down to 2x1 pixel window for digital zoom. subsampling reduces resolution while maintaining the constant field of view. the analog video output of the pixel array is processed by an on-chip analog signal pipeline. double sampling (ds) eliminates the fixed pattern noise. the programmable gain and offset amplifier maps the signal swing to the adc input range. a 10-bit adc converts the analog data to a 10-bit digital word stream. the sensor uses a three-wire serial-parallel (spi) interface. it operates with a single 2.5 v power supply and requires only one master clock for operation up to 40 mhz. it is housed in a 68-pin ceramic lcc package. this data sheet enables the development of a camera system, based on the described timing and interfacing given in the following sections. ordering information marketing part number description package NOII4SM6600A-qdc mono with glass 68 pin lcc note: for more information, see ordering code definition on page 29. http://onsemi.com figure 1. ibis4 ? 6600 image sensor
NOII4SM6600A http://onsemi.com 2 contents features 1 ..................................... applications 1 ................................. description 1 .................................. ordering information 1 ......................... contents 2 .................................... specifications 3 ................................ general specifications 3 ......................... electro optical specifications 3 ................... spectral response curve 4 ...................... electro voltaic response curve 5 ................ electrical specifications 6 ...................... sensor architecture 7 ........................... floor plan 7 ................................. pixel 8 ..................................... output amplifier 8 ............................ analog to digital converter 11 ................... serial to parallel interface (spi) 11 ................ sensor operation 12 ............................. pixel rate 12 ................................. region of interest (roi) read out 12 .............. subsampling modes 12 ......................... electronic shutter 15 ........................... high dynamic range modes 16 .................. sequencer and registers 17 ....................... description of registers 19 ...................... timing diagrams 23 ............................. sequencer control signals 23 .................... basic frame and line timing 23 .................. pixel output timing 24 ......................... adc timing 25 ............................... package information 26 .......................... pin list description 26 ......................... package outline drawing 29 ..................... mechanical specifications 30 ...................... glass lid 31 .................................. handling precautions 31 ......................... limited warranty 31 ............................ return material authorization (rma) 31 ........... acceptance criteria specification 31 ............... ordering code definition 31 ...................... acronyms 32 ................................... glossary 33 ....................................
NOII4SM6600A http://onsemi.com 3 specifications general specifications parameter specification remarks pixel architecture 3t-pixel pixel size 3.5 m x 3.5 m the resolution and pixel size results in a 7.74 mm x 10.51 mm optical active area. resolution 2210 x 3002 pixel rate 40 mhz using a 40 mhz system clock and 1 or 2 parallel outputs shutter type electronic rolling shutter full frame rate 5 frames/second increases with roi read out and/or subsampling electro optical specifications parameter specification remarks fpn (local) <0.20%, 2 lsb10 %rms of saturation signal prnu (local) <1.5% rms of signal level conversion gain 43 v/e - at output (measured) output signal amplitude 0.6 v at nominal conditions saturation charge 21500 e - sensitivity (peak) 411 v.m 2 /w.s 4.83 v/lux.s at 650 nm (85 lux = 1 w/m 2 ) sensitivity (visible) 328 v.m 2 /w.s 2.01 v/lux.s 400-700 nm (163 lux = 1 w/m 2 ) peak qe * ff peak spectral response 25% 0.13 a/w average qe*ff = 22% (visible range) average sr*ff = 0.1 a/w (visible range) see the section spectral response curve on page 4. fill factor 35% light sensitive part of pixel (measured) dark current 3.37 mv/s 78 e-/s typical value of average dark current of the whole pixel array (at 21 c) dark signal non uniformity 8.28 mv/s 191 e-/s dark current rms value (at 21 c) temporal noise 24 rms e- measured at digital output (in the dark) signal/noise ratio 895:1 (40 db) measured at digital output (in the dark) dynamic range 59 db spectral sensitivity range 400 - 1000 nm optical cross talk 15% 4% to the first neighboring pixel to the second neighboring pixel power dissipation 225 mw typical (including adcs)
NOII4SM6600A http://onsemi.com 4 spectral response curve 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 400500600700800900?1000 wavelenght [nm] spectral response [a/w] qe 10% qe 20% qe 30% figure 2. spectral response curve figure 2 shows the characteristics of the spectral response. the curve is measured directly on the pixels. it includes the effects of nonsensitive areas in the pixel, for example, interconnection lines. the sensor is light sensitive between 400 and 1000 nm. the peak qe x ff is 25% approximately 650 nm. in view of a fill factor of 35%, the qe is close to 70% between 500 and 700 nm.
NOII4SM6600A http://onsemi.com 5 electro voltaic response curve figure 3. electro voltaic response curve 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 # electrons output swing [v] 5000 10000 15000 20000 25000 figure 3 shows the pixel response curve in linear response mode. this curve is the relation between the electrons detected in the pixel and the output signal. the resulting voltage-electron curve is independent of any parameters, for example, integration time. the voltage to electrons conversion gain is 43 v/electron. table 1. features and general specifications feature specification/description electronic shutter type rolling shutter integration time control 60 s - 1/frame period windowing (roi) randomly programmable roi read out sub sampling modes several sub sample modes can be programmed (refer table 8 on page 12) extended dynamic range dual slope (up to 90 db optical dynamic range) and nondestructive read out mode analog output the output rate of 40 mpixels/s can be achieved with two analog outputs, each working at 20 mpixel/s digital output two on-chip 10-bit adcs at 20 msamples/s are multiplexed to one digital 10-bit output at 40 msamples/s supply voltage v dd nominal 2.5 v (some supplies require 3.3 v for extended dynamic range) logic levels 2.5 v interface serial peripheral interface (spi) package 68-pin lcc
NOII4SM6600A http://onsemi.com 6 electrical specifications table 2. recommended operating ratings (notes 1 and 3) symbol description min max units t j operating temperature range -30 65 c table 3. absolute maximum ratings (notes 2, 3 and 4) symbol parameter min max units v dd (note 5) dc supply voltage ?0.5 4.3 v v in dc input voltage ?0.5 (v dd + 0.5) v v out dc output voltage ?0.5 (v dd + 0.5) v t s (note 3) storage temperature ?30 +85 c %rh humidity (relative) - 85% at 85 c electrostatic discharge (esd) human body model (hbm) (note 3) v charged device model (cdm) lu latch-up (note 4) ma 1. operating ratings are conditions in which operation of the device is intended to be functional. all parameters are characteri zed for dc conditions after thermal equilibrium is established. unused inputs must always be tied to an appropriate logic level, for example, vdd or gnd. 2. stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyo nd those specified is not implied. 3. this device does not contain circuitry to protect the inputs against damage caused by high static voltages or electric fields . on semiconductor recommends that customers become familiar with, and follow the procedures in jedec standard jesd625 ? a. refer to application note an52561. 4. the ibis4 ? 6600 does not have latchup protection. 5. v dd = v ddd = v dda (v ddd is supply to digital circuit, v dda to analog circuit). all parameters are characterized for dc conditions after thermal equilibrium is established. unused inputs must always be tied to an appropriate logic level, for example, v dd or gnd. the ibis4-6600 is extremely susceptible to noise on the power supplies. in addition, it has no power supply filtering on chip. therefore, all power supplies to the sensor must be clean with the target being to achieve a low noise (1 mv). special attention must be given to the pixel supplies vpix, gnd_ab, vreset and vreset_ds. table 4. recommended dc operating conditions parameter description typical dynamic currents min typ (v) max vdd_pix v dd of pixel core -5% 2.5 v 5% vdd_reset reset voltage. highest voltage to the chip. 3.3v for extended dynamic range or ?hard reset? -5% 2.5 v 3.3 v vdd_reset_ds variable reset voltage (dual slope) -5% 2.5 v 5% vdda v dd of analog supply 3 ma -5% 2.5 v 5% vdda_adc analog supply to the adc 53 ma -5% 2.5 v 5% vddamp v dd of analog output. (can be connected to v dda ) 20 ma -5% 2.5 v 5% vddd v dd of digital supply 3 ma -5% 2.5 v 5% vddd_adc digital supply to the adc 10 ma -5% 2.5 v 5%
NOII4SM6600A http://onsemi.com 7 sensor architecture floor plan re s e t select analog output (2) eos _yl eos _yr tr i l tr i r dac in adc , 10 bit adc , 10 bit sequencer image core sensor spi pixel array addres s able x ? s hift regis ter + s ub ? s ampling addres s able y ? shift register + sub ? s ampling column ampli ? ers re s e t a nd s e le c t drive rs re s e t a nd s e le c t drive rs clk_y sync_yl pixel (0,0) dac addressable y ? shift register + sub ? sampling clk_y r sync_y dig. logic dig. logic address & da ta bus figure 4. floor plan 2210 x 3002 (excl. dark + dummy pixels) figure 4 shows the architecture of the designed image sensor. it consists of the pixel array, shift registers for the readout in x and y direction, parallel analog output amplifiers, and column amplifiers that correct for the fixed pattern noise caused by threshold voltage nonuniformities. reading out the pixel array starts by applying a y clock pulse to select a new row, followed by a calibration sequence to calibrate the column amplifiers (row blanking time). depending on external bias resistors and timing, typically this sequence takes about seven seconds every line (baseline). this sequence is necessary to remove the fixed pattern noise of the pixel and of the column amplifiers themselves (by a double sampling technique). pixels can also be read out in a nondestructive manner. two dacs are added to make the offset level of the pixel values adjustable and equal for the two output buses. a third dac is used to connect the buses to a stable voltage during the row blanking period, or reset the buses continuously in case of a nondestructive readout. two 10-bit adcs running at 20 msamples/s convert the analog pixel values. the digital outputs are multiplexed to one digital 10-bit output at 40 msamples/s. note that these blocks are electrically completely isolated from the sensor part, except for the multiplexer, for which the settings are uploaded through the shared address and data bus. the x and y shift registers have a programmable starting point. the possibilities of the starting point are limited because of limitations imposed by subsampling requirements. the start address is uploaded through the serial to parallel interface. most of the signals for the image core shown in figure 4 are generated on-chip by the sequencer. this sequencer also allows running the sensor in basic modes, not fully autonomous.
NOII4SM6600A http://onsemi.com 8 pixel architecture the pixel architecture is the classic three-transistor pixel, as shown in figure 5. the pixel is implemented using the high fill factor technique patented by fillfactory (us patent no. 6,225,670 and others) figure 5. 3t pixel architecture selec vdd m1 m2 m3 reset output (column) select fpn and prnu fixed pattern noise correction is done on-chip. raw images taken by the sensor typically feature a residual (local) fpn of 0.35% rms of the saturation voltage. the photo response non uniformity (prnu), caused by the mismatch of photodiode node capacitances, is not corrected on chip. measurements indicate that the typical prnu is about 1.5% rms of the signal level. dark and dummy pixels figure 6 shows a plan of the pixel array. the sensor is designed in portrait orientation. a ring of dummy pixels surrounds the active pixels. black pixels are implemented as ?optical? black pixels. figure 6. floor plan pixel array dummy ring of pixels , surrounding complete pixel a rra y. not re a d ring of 2 dummy pixels , illuminate d, readable array of active pixels , read 3002x 2210 ring of dummy pixels , covered with black layer, readable 2222 3014 2210 3002 output amplifier the output amplifier subtracts the reset and signal voltages from each other to cancel fpn as much as possible (shown in figure 7). the dac that is used for offset adjustment consists of two dacs. one dac is used for the main offset (dac_raw). the other enables fine tuning to compensate the offset difference between the signal paths arriving at the two amplifiers a1 and a2 (dac_fine). with the analog multiplexer, the signals s1 and s2 from the two buses can be combined to one pixel output at full pixel rate (40 mhz). however, the two analog signals s1 and s2 can also be available on two separate output pins to allow a higher pixel rate. the third dac (dac_dark) puts its value on the buses during the calibration of the output amplifier. in case of nondestructive readout (no double sampling), bus1_r and bus2_r are continuously connected to the output of the dac_fine to provide a reference for the signals on bus1_s and bus2_s. the complete output amplifier can be put in standby by setting the corresponding bit in the amplifier register.
NOII4SM6600A http://onsemi.com 9 figure 7. output amplifier architecture ? + ? + bus1_r bus1?s bus2_r bus2?s dac_raw / dac_fine pixel output pixel output 2 programmable gain amplifiers a2 a1 s2 s1 1 1 dac_dark stage 1 stage 2 stage 3 output drivers analog multiplexer stage 1: offset, fpn correction, and multiplexing in the first stage, the signals from the buses are subtracted and the offset from the dacs is added. after a system reset, the analog multiplexer is configured for two outputs (see the bit settings in the amplifier register on page 22. ) in case one_out is set to 1, the two signals s1 and s2 are multiplexed to one output (output 1). the amplifiers of stage 2 and stage 3 of the second output path are then put in standby. the speed and power consumption of the first stage can be controlled through the resistor connected to cmd_out_1. stage 2: programmable gain amplifier the second stage provides the gain, which is adjustable between 1.36 and 17.38 in steps of approximately 20.25 (~1.2). an overview of the gain settings is given in table 5. the speed and power consumption of the second stage can be controlled through the resistor connected to cmd_out_2. table 5. pga gain settings bits dc gain bits dc gain 0000 1.36 1000 5.40 0001 1.64 1001 6.35 0010 1.95 1010 7.44 0011 2.35 1011 8.79 0100 2.82 1100 10.31 0101 3.32 1101 12.36 0110 3.93 1110 14.67 0111 4.63 1111 17.38 stage 3: output drivers the speed and power consumption of the third stage can be controlled through the resistor connected to cmd_out_3. the output drivers are designed to drive a 20 pf output load at 40 msamples/s with a bias resistor of 100 k . offset dacs figure 8 shows how the dac registers influence the black reference voltages of the two different channels. the offset is mainly given through dac_raw. dac_fine can be used to shift the reference voltage of bus 2 up or down to compensate for different offsets in the two channels.
NOII4SM6600A http://onsemi.com 10 figure 8. offset for the two channels through dac_raw and dac_fine dac_raw d ac _ raw _ reg <0:7 out dac_fine vdda out 10k 200k 50k 50k 10k 200k blackref bus1 blackref bus2 gnda d ac _ fine _ reg <0:7 rcal rcal pad rcal _ dac _ out floating rcal vcal + note that in this figure, ?k? represents k assume that v outfull is the voltage that depends on the bit values that are applied to the dac and ranges from: v outfull :0( bit values 00000000) vdda 1 1 2 8 ( bit values 11111111) externally, the output range of dac_raw can be changed by connecting a resistor rcal to rcal_dac_out and applying a voltage v cal . the output voltage v out of dac_raw follows the relation (r = 10 k ). v out r r cal 2 r r cal v outfull r 2 r r cal v cal special case: r cal = ?open? (infinite resistance), then v out = v outfull (for example, for dac_fine) rcal = 0 ohms ?short? and vcal = gnd, then v out = v outfull /2
NOII4SM6600A http://onsemi.com 11 analog to digital converter the ibis4-6600 has a two 10-bit flash analog digital converters. the adcs are electrically separated from the image sensor. the inputs of the adc must be tied externally to the outputs of the output amplifiers. one adc samples the even columns and the second adc samples the odd columns. alternatively, one adc can also sample all the pixels. the sensor?s outputs are not designed to drive large loads. therefore, to drive a cable or long pcb trace, the outputs of the sensor should be buffered. table 6. adc specifications parameter specification input range set by external resistors (refer the section the internal resist- ance has a value of approximately 577 . only 277 of this internal resistance is actually used as reference for internal adc.) quantization 10 bits nominal data rate 20 msamples/s dnl typical: 1.5 lsb10 inl typical: 5 lsb10 input capacitance < 2 pf conversion law linear/gamma corrected the internal resistance has a value of approximately 577 . only 277 of this internal resistance is actually used as reference for the internal adc. black calibration due to slight variations in the chip fabrication process, the output analog voltage of the pga is not perfectly matched to the input analog range of the adc. as a result, a reduced dynamic range is obtained when comparing sensors/cameras from different lots. this is especially true in the dark as it is possible that a part of the analog range gets clipped when it reaches the adc. for this reason, black calibration step is required. because this is a fixed setting, and varies very slightly with temperature, the setting can be done at the factory itself. while grabbing normal images, the settings can be loaded from an on-board memory. in the ibis4-6600 image sensor, black calibration step also tries to match the output of the odd and even channels. the steps for black calibration are - 1. put the sensor in dark. 2. change dac_raw such that no pixel or least number of pixels (assuming there are defect pixels) have a zero adc output value. 3. change dac_fine such that the average of the odd columns is almost same as the even columns. 4. change dac_raw again such that all pixels have a non-zero output, but are as close to zero as possible. 5. record the dac_raw and dac_fine values. 6. load the recorded dac register values during operation. serial to parallel interface (spi) to upload the sequencer registers, a dedicated serial to parallel interface (spi) is implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. the address must be uploaded first (msb first), then the data (also msb first). the elementary unit cell is shown in figure 9. sixteen of these cells are connected in series, having a common spi_clk form the entire uploadable parameter block. dout of one cell is connected to spi_data of the next cell (maximum speed is 20 mhz). the uploaded settings on the address/data bus are loaded into the correct register of the sensor on the rising edge of signal reg_clock and become effective immediately. figure 9. spi interface d q c d q c spi_data to address/data bus dout spi_clk reg_clock 16 outputs to address/data bus spi_clk spi_data unity c ell entire upl oadable address block a reg_clock a 3a1 2 reg_clock spi_clk internal register upload spi_data d0
NOII4SM6600A http://onsemi.com 12 sensor operation pixel rate the pixel rate for this sensor is high enough to support a frame rate greater than 75 hz for a window size of 640 x 480 pixels (vga format). w ith a row blanking time of 7.2 s (as baseline, refer the following calculations), requires a minimum pixel rate of approximately 40 mhz. the bandwidth of the column amplifiers, gain amplifiers and output stage are determined by external bias resistors. taking into account a pixel rate of 40 mhz, a full frame rate of a little more than 5 frames/s is obtained the frame period of the ibis4-6600 sensor is calculated as: => frame period = (nr . lines * (rbt + pixel period * nr. pixels)) in this equation: nr. lines: number of lines read out each frame (y) nr. pixels: number of pixels read out each line (x) rbt: row blanking time = 7.2 s (typical) pixel period: 1/40 mhz = 25 ns example: read out time of the full resolution at nominal speed (40 mhz pixel rate): => frame period = (3002 * (7.2 s + 25 ns * 2210)) = 187.5 ms => 5.33 fps. region of interest (roi) read out windowing is easily achieved by uploading the starting point of the x and y-shift registers in the sensor registers (refer t able 11 on page 17). this downloaded starting point initiates the shift register in the x and y-direction, triggered by the y_start (initiates the y-shift register) and the y_clk (initiates the x-shift register) pulse. the minimum step size for the x-address and y-address is 24 pixels. the frame rate increases in an almost linear manner when fewer pixels are read out. table 7 lists the achievable frame rates with roi read out. table 7. frame rate vs. resolution image resolution (y*x) frame rate [frames/s] frame readout time [ms] comment 3002 x 2210 5 187.5 full resolution 1501 x 1104 14 67 roi read out 640 x 480 89 11 11 subsampling modes to increase the frame rate for lower resolution and regions of interest, several sub sampling modes are implemented. the possible sub sample modes are listed in table 8. the bits can be programmed in the image_core register (refer table 11 on page 17). two adjacent pixels are read in any mode. the number of pixels that is not read varies from mode to mode. this is designed as a repeated block 24 pixels wide, which is the lowest common multiple of the modes described. including the dummy pixels and the two additional rows/columns, the number of starting coordinates for the x and y shift register is 99 in the x direction and 138 in the y direction. the total number of pixels, excluding dummy pixels, is a multiple of 24, and two additional pixels to have the same window edges independently of the sub sampling mode. in the x direction, two columns are always addressed at the same moment, because the signals from the odd and even columns must be put simultaneously on the corresponding bus. in the y direction, the rows are addressed one by one. this results in slightly different implementations of the sub-sampling modes for the two directions (refer figure 10 and figure 11 on page 14). table 8. subsample patterns mode bits read step description a 000 2 2 default mode b 001 2 4 (skip 2) c 010 2 6 (skip 4) d 011 2 8 (skip 6) e 1xx 2 12 (skip 10)
NOII4SM6600A http://onsemi.com 13 a b c d e shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns 24 column amplifiers bus1_s bus1_r bus2_s bus2_r scan direction figure 10. x ? sub sampling
NOII4SM6600A http://onsemi.com 14 figure 11. y ? sub sampling g shift re isters on pixel pitch gg lo ic selectin 1 row a b c d e scan direction table 9. frame rate vs. sub sample mode mode ratio resolution (y*x) frame time [ms] frame time [ms] a 1:1 3002 x 2210 187.4 5.3 b 1:4 1502 x 1106 52.3 19.1 c 1:9 1002 x 738 25.7 38.9 d 1:16 752 x 554 15.8 63.2 63.2 1:36 502 x 370 8.2 121.2 vga (p) 640 x 480 12.3 81.5 vga (p) + 23 663 x 503 13.1 76.4 vga (l) 480 x 640 11.1 89.9 vga(l) + 23 503 x 663 11.9 83.7
NOII4SM6600A http://onsemi.com 15 electronic shutter an electronic shutter similar to a rolling curtain is implemented on-chip. as shown in figure 13, there are two y shift registers. one shift register points to the row that is currently being read out. the other shift register points to the row that is currently being reset. both pointers are shifted by the same y-clock and move over the focal plane. the integration time is set by the delay between both pointers. figure 12. electronic shutter integration time readout pointer reset pointer in case of a mechanical shutter, the two shift registers can be combined to simultaneously apply the pulses from both sides of the pixel array. this is to halve the influence of the parasitic rc times of the reset and select lines in the pixel array. this can result in a reduction of the row blanking time. this is the case when fast_reset in the sequencer register is set to 1, or in the nondestructive readout modes 1 and 2. time axis line number reset sequence frame time integration time figure 13. electronic rolling shutter operation
NOII4SM6600A http://onsemi.com 16 high dynamic range modes double slope integration the ibis4-6600 has a feature called double slope integration to increase the optical dynamic range of the sensor. the pixel response can be extended over a larger range of light intensities by using a ?dual slope integration?. this is obtained by adding charge packets from a long and a short integration time in the pixel during the same exposure time. figure 14 shows the response curve of a pixel in dual slope integration mode. the curve also shows the response of the same pixel in linear integration mode at the same light levels, with a long and short integration time. dual slope integration is obtained by feeding a lower supply voltage to vdd_reset_ds (for example, apply 2.0 v). note that for normal (single slope) operation, vdd_reset_ds must have the same value as vdd_reset. the difference between vdd_reset_ds and vdd_reset determines the range of the high sensitivity, and as a result the output signal level at which the transition between high and low sensitivity occurs. put the amplifier gain to the lowest value where the analog output swing covers digital input swing of the adc. increasing the amplification too much may boost the high sensitivity part over the whole adc range. the electronic shutter determines the ratio of integration times of the two slopes. the high sensitivity ramp corresponds to ?no electronic shutter?, thus maximal integration time (frame read out time). the low sensitivity ramp corresponds to the electronic shutter value that is obtained in normal operation. figure 14. double slope response 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0%20%? 40%? 60%? 80%?100% relative exposure (arbitrary scale) out put signal [v] dual slope operation long integration time short integration time nondestructive read out (ndr) the default mode of operation of the sensor is with fpn correction (double sampling). however, the sensor can also be read out in a nondestructive method. after a pixel is initially reset, it can be read multiple times, without being reset. the initial reset level and all intermediate signals can be recorded. high light levels saturate the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, use the later or latest samples. essentially an active pixel array is read multiple times, and reset only once. the external system intelligence interprets the data. table 10 on page 17 summarizes the advantages and disadvantages of nondestructive readout. figure 15. principle of nondestructive read out time
NOII4SM6600A http://onsemi.com 17 table 10. ndr: advantages and disadvantages advantages disadvantages low noise, because it is true cds. in the order of 10 e- or below. system memory required to record the reset level and the intermediate samples. high sensitivity, because the conversion capacitance is kept rather low. requires multiples readings of each pixel, thus higher data throughput. high dynamic range, because the results include signals for short and long integrations times. requires system level digital calculations. sequencer and registers figure 4 on page 7 showed several control signals that are needed to operate the sensor in a particular sub sampling mode, with a certain integration time, output amplifier gain, and more. most of these signals are generated on-chip by the sequencer that uses only a few control signals. these control signals must be generated by the external system ? sys_clock, which defines the pixel rate (nominal 40 mhz), ? y_start pulse, which indicates the start of a new frame, ? y_clock, which selects a new row and starts the row blanking sequence, including the synchronization and loading of the x-register. the relative position of the internal pulses is determined by a number of data bits that are uploaded in internal registers through a serial to parallel interface (spi). internal registers table 11 lists the internal registers with a short description. the registers are discussed in more detail in the following sections. on power-on, all the internal register of the ibis4-6600 are reset to 0. all the sensor registers must to be loaded before the sensor is brought out of reset. table 11. list of internal registers register bit name description 0 (0000) 11:0 sequencer register selection of mode, granularity of the x sequencer clock, calibration, default value <11:0>:?000100000000? 0 ndr mode of readout: ndr = 0: normal readout (double sampling) ndr = 1: non-destructive readout 1:2 ndr_mode 4 different modes of nondestructive readout (no influence if ndr = 0) 3 reset_black 0 = normal operation 1 = reset of pixels before readout 4 fast_reset 0 = electronic shutter operation 1 = addressing from both sides 5 frame_cal_mode 0 = fast 1 = slow 6 line_cal_mode 0 = fast 1 = slow 7 cont_charge 0 = normal mode 1 = continuous precharge 8 gran_x_seq_lsb granularity of the x sequencer clock 9 gran_x_seq_msb 10 black 0 = normal mode 1 = disconnects column amplifiers from buses, output of amplifier equals dark refer- ence level 11 reset_all 0 = normal mode 1 = continuous reset of all pixels
NOII4SM6600A http://onsemi.com 18 table 11. list of internal registers register description name bit 1 (0001) 10:0 nrof_pixels number of pixels to count (x direction). max. 2222/2 (2210 real + 12 dummy pixels). default value <10:0>:?01000000000? 2 (0010) 11:0 nrof_lines number of lines to count (y direction) max. 3014 (3002 real + 12 dummy pixels) default value <11:0>:?101111000110? 3 (0011) 11:0 int_time integration time default value <11:0>:?000000000001? 4 (0100) 7:0 delay delay of sequencer pulses default value <7:0>:?00000011? 0:3 delay_pix_valid delay of pix_valid pulse 4:7 delay_eol/eof delay of eol/eof pulses 5 (0101) 6:0 x_reg x start position (0 to 98) default value <6:0>:?0000000? 6 (0110) 7:0 y_reg y start position (0 to 137) default value <7:0>:?00000000? 7 (0111) 7:0 image core register default value <7:0>:?00000000? 1:0 test_mode lsb: odd, msb: even 0 = normal operation 4:2 x_subsample sub sampling mode in x-direction 7:5 y_subsample sub sampling mode in x-direction 8 (1000) 9:0 amplifier register default value <9:0>:?0000010000? 3:0 gain<3:0> output amplifier gain setting 4 unity 0 = gain setting by gain<3:0> 1 = unity gain setting 5 one_out 0 = two analog outputs 1 = multiplexing to one output (out_1) 6 standby 0 = normal operation 1 = amplifier in standby mode 7:9 delay_clk_amp delay of pixel clock to output amplifier 9 (1001) 7:0 dac_raw_reg amplifier dac raw offset default value <7:0>:?10000000? 10 (1010) 7:0 dac_fine_reg amplifier dac fine offset default value <7:0>:?10000000? 11 (1011) 7:0 dac_dark_reg dac dark reference on output bus default value <7:0>:?10000000? 12 (1100) 10:0 adc register default value <10:0>:?00000000000? 0 standby_1 0 = normal operation 1 = adc in standby 1 standby_2 2 one 0 = multiplexing of two adc outputs 1 = disable multiplexing 3 switch if one = 0: delay of output with one (ext_clk = 0) or half (ext_clk = 1) clock cycle if one = 1: switch between two adcs
NOII4SM6600A http://onsemi.com 19 table 11. list of internal registers register bit name description 12 (1100) 4 ext_clk 0 = internal clock (same as clock to x shift register and output amplifier) 1 = external clock 5 tristate 0 = normal operation 1 = outputs in tristate mode 6:8 delay_clk_adc delay of clock to adcs and digital multiplexer 9 gamma 0 = linear conversion 1 = ?gamma? law conversion 10 bitinvert 0 = no inversion of bits 1 = inversion of bits 13 (1101) reserved 14 (1110) reserved 15 (1111) reserved description of registers sequencer register a. ndr (bit 0) in normal operation (ndr = 0), the sensor operates in double sampling mode. at the start of each row readout, the signals from the pixels are sampled, the row is reset, and the signals from the pixels are sampled again. the values are subtracted in the output amplifier. when ndr is set to 1, the sensor operates in nondestructive readout (ndr) mode (refer table 12). b. ndr_mode (bit 1 and 2) these bits only influence the operation of the sensor in case ndr (bit 0) is set to 1. there are two modes for nondestructive readout (mode 1 and 2). each mode needs two different frame readouts (setting 1 and 2 for mode 1, setting 3 and 4 for mode 2). a reset/readout sequence (reset_seq) and then one or several pure readout sequences (called read_seq hereafter). table 12 gives an overview of the different ndr modes. table 12. overview of ndr modes setting bits ndr mode sequence 1 00 1 reset 2 01 1 read 3 10 2 reset 4 11 2 read mode 1 in this mode, the sensor is readout in the same method as for the nondestructive readout. however, electronic shutter control is not possible in this case, that is, the minimal (integration) time between two readings is equal to the number of lines that has to be read out (frame read time). the row lines are clocked simultaneously (left and right clock pulses are equal). mode 2 in this mode, it is possible to have a shorter integration time than the frame read time. rows are alternatingly read out with the left and right pointer. these two pointers can point to two different rows (see int_time register). the integration time between two readings of the same row is equal to the number of lines that is set in the int_time register multiplied by 2 plus 1, and is the minimal one line read time. in setting 3, the row that is read out by the left pointer is reset and read out (first y_clock), and the row that is read out by the right pointer is read out without being reset (second y_clock). in setting 4, both rows are read out without being reset (on the first y_clock the row is read out by the left pointer; on the second y_clock the row is read out by the right pointer). for both modes, the signals are read out through the same path as with destructive readout (double sampling), but the buses that are carrying the reset signals in destructive readout, are set to the voltage given by dac_dark in nondestructive readout. c. reset_black (bit 3) if reset_black is set to 1, each line is reset before it is read out (except for the row that is read out by the right pointer in ndr mode 2). this may be useful to obtain black pixels. d. fast_reset (bit 4) the fast reset option (fast_reset = 1) might be useful in case a mechanical camera shutter is used. the fast reset is done on a row-by-row basis, not by a global reset. a global reset means charging all the pixels at the same time, which may result in a huge peak current. therefore, the rows can be scanned rapidly while the left and right shift registers are both controlled identically, so that the reset lines over the pixel array are driven from both sides. this reduces the reset (row blanking) time (when fast_reset = 1 the smallest x-granularity can be used). after the row blanking time, the
NOII4SM6600A http://onsemi.com 20 row is reset and y_clock can be asserted to reset the next row. after a certain integration time, the read out can be done in a similar method. the y shift registers are again synchronized to the first row. both shift registers are driven identically, and all rows and columns are scanned for (destructive) readout. fast_reset = 1 puts the sequencer in such mode that the left and right shift registers are both controlled identically. e. output amplifier calibration (bit 5 and 6) bits frame_cal_mode and line_cal_mode define the calibration mode of the output amplifier. during every row-blanking period, a calibration is done of the output amplifier. there are two calibration modes. the fast mode (= 0) can force a calibration in one cycle. however, it is not accurate and suffers from ktc noise, while the slow mode (= 1) can only make incremental adjustments and is noise free. approximately 200 or more ?slow? calibrations have the same effect as one ?fast? calibration. different calibration modes can be set at the beginning of the frame (frame_cal_mode bit) and for every subsequent row that is read (line_cal_mode bit). f. continuous charge (bit 7) for some applications, it might be necessary to use continuous charging of the pixel columns instead of a precharge on every row sample operation. setting bit cont_charge to 1 activates this function. the resistor connected to pin cmd_col is used to control the current level on every pixel column. g. internal clock granularities the system clock is divided several times on-chip. the x-shift-register that controls the column/pixel readout, is clocked by half the system clock rate. odd and even pixel columns are switched to two separate buses. in the output amplifier, the pixel signals on the two buses can be combined to one pixel stream at 40 mhz. the clock that drives the x-sequencer can be a multiple of 2, 4, 8, or 16 times the system clock. table 13 lists the settings for the granularity of the x-sequencer clock and the corresponding row blanking time (for ndr = 0). a row blanking time of 7.18 s is the baseline for almost all applications. table 13. granularity of x-sequencer clock and corresponding row blanking time (for ndr = 0) gran_x_seq_msb/lsb x-sequencer clock row blanking time row blanking time [ s] 00 2 x sys_clock 142 x tsys_clock 3.55 01 4 x sys_clock 282 x tsys_clock 7.05 10 8 x sys_clock 562 x tsys_clock 14.05 11 16 x sys_clock 1122 x tsys_clock 28.05 h. black (bit 10) if black is set to 1, the internal black signal is held high continuously. as a result, the column amplifiers are disconnected from the buses, and the buses are set to the voltage given by dac_dark. the output of the amplifier equals the voltages from the offset dacs. i. reset_all (bit 11) if reset_all is set to 1, all the pixels are simultaneously put in a ?reset? state. in this state, the pixels behave logarithmically with light intensity. if this state is combined with one of the ndr modes, the sensor can be used in a nonintegrating, logarithmic mode with high dynamic range. j. nrof_pixels register after the internal x_sync is generated (start of the pixel readout of a particular row), the pixel_valid signal goes high. the pixel_valid signal goes low when the pixel counter reaches the value loaded in the nrof_pixel register and an eol pulse is generated. due to the fact that two pixels are addressed at each internal clock cycle, the amount of pixels read out in one row is 2*(nrof_pixel + 1). k. nrof_lines register after the internal yl_sync is generated (start of the frame readout with y_start), the line counter increases with each y_clock pulse until it reaches the value loaded in the nrof_lines register and an eof pulse is generated. in ndr mode 2, the line counter increments only every two y_clock pulses and the eof pulse shows up only after the readout of the row indicated by the right shift register int_time register when the y_start pulse is applied (start of the frame readout), the sequencer generates the yl_sync pulse for the left y-shift register. this loads the left y-shift register with the pointer loaded in y_reg register. at each y_clock pulse, the pointer shifts to the next row and the integration time counter increases (increment only every two y_clock pulses in ndr mode 2) until it reaches the value loaded in the int_time register. at that moment, the yr_sync pulse for the right y-shift register is generated, which loads the right y -shift register with the pointer loaded in y_reg register (shown in figure 16 on page 21).
NOII4SM6600A http://onsemi.com 21 figure 16. syncing of y ? shift registers line n t reg_int last line, followed by sync of left shift-register t int c syn sync of right shift-register sync of left shift-register treg_int: difference between left and right pointer = integration counter until value in int_time register is reached = int_time register. in case of ndr = 0, the actual integration time tint is given by tintl: integration time [# lines] = nrof_lines register ? int_time register + 1 in case of ndr = 1, ndr mode 1, the time tint between two readings of the same row is given by: tint:integration time [# lines] = nrof_lines register + 1 in case of ndr = 1, ndr mode 2, the times tint1 and tint2 between two readings of the same row (alternatingly) are given by: tint1: integration time [# lines] = 2 * int_time register +1 tint2: integration time [# lines] = 2 * (nrof_lines . register + 1) - (2 * int_time register + 1) delay register the delay register can be used to delay the pixel_valid pulse (bits 0:3) and the eol/eof pulses (bits 4:7) to synchronize them to the real pixel values at the analog output or the adc output (which give additional delays depending on their settings). the bit settings and corresponding delay are indicated in table 14. table 14. added delay by changing the delay register settings bits delay [# sys_clock periods] bits delay [# sys_clock periods] 0000 0 1000 6 0001 0 1001 7 0010 0 1010 8 0011 1 1011 9 0100 2 1100 10 0101 3 1101 11 0110 4 1110 12 0111 5 1111 13 x_reg register the x_reg register determines the start position of the window in the x-direction. in this direction, there are 2208 + 2 + 12 readable pixels. in the active pixel array, sub sampling blocks are 24 pixels wide and the columns are read two by two. therefore, the number of start positions equals 2208/24 +2/2 +12/2 = 92 + 1 + 6 = 99. y_reg register the y_reg register determines the start position of the window in the y-direction. in this direction, there are 3000 + 2 + 12 readable pixels. in the active pixel array, sub sampling blocks are 24 pixels wide and the rows are read one by one. therefore, the number of start positions equals 3000/24 + 2/2 +12 = 125 + 1 + 12 = 138. image_core register bits 0:1 of the image_core register defines the several test modes of the image core. setting 00 is the default and normal operation mode. if the bit is set to 1, the odd (bit 0) or even (bit 1) columns are tight to v dd . these test modes can be used to tune the sampling point of the adcs to an optimal position. bits 2:7 of the image_core register define the sub sampling mode in the x-direction (bits 2:4) and in the y-direction (bits 5:7). the sub sampling modes and corresponding bit setting are shown in ?subsamling modes? on page 12. amplifier register a. gain (bits 0:3) the gain bits determine the gain setting of the output amplifier. they are effective only if unity = 0. the gains and corresponding bit setting are given in table 5 on page 9.
NOII4SM6600A http://onsemi.com 22 b. unity (bit 4) if unity = 1, the gain setting of gain is bypassed and the gain amplifier is put in unity feedback. c. one_out if one_out = 0, the two output amplifiers are active. if one_out = 1, the signals from the two buses are multiplexed to output out1. the gain amplifier and output driver of the second path are put in standby. d. standby if standby = 1, the complete output amplifier is put in standby. this reduces the power consumption significantly. e. delay_clk_amp the clock that acts on the output amplifier can be delayed to compensate for any delay that is introduced in the path from shift register, column selection logic, column amplifier, and buses to the output amplifier. setting ?000? is used as a baseline. table 15. added delay by changing the delay_clk_amp bit settings bits delay [ns] bits delay [ns] 000 1.7 100 inversion + 8.3 001 2.9 2.9 inversion + 9.7 010 4.3 110 inversion + 11.1 011 6.1 111 inversion + 12.3 dac_raw_reg and dac_fine_reg register these registers determine the black reference level at the output of the output amplifier. bit setting 1 1111111 for dac_raw_reg register gives the highest offset voltage; bit setting 00000000 for dac_raw_reg register gives the lowest offset voltage. ideally, if the two output paths have no offset mismatch, the dac_fine_reg register must be set to 10000000. deviation from this value can be used to compensate the internal mismatch (see the section offset dacs on page 9). dac_raw_dark register this register determines the voltage level that is put on the internal buses during calibration of the output stage. this voltage level is also continuously put on the reset buses in case of nondestructive readout (as a reset level for the double sampling fpn correction). adc register a. standby_1 and standby_2 if only one or none of the adcs is used, the other or both adcs can be put in standby by setting the bit to 1. this significantly reduces the power consumption. b. one if out1 and out2 are both used and connected to adc_in1 and adc_in2 respectively, one must be 0 to use both adcs and to multiplex their output to adc_d<9:0>. if one = 1, the multiplexing is disabled. c. switch if the two adcs are used (one = 0) and internal pixel clock (ext_clk = 0), the adc output is delayed with one system clock cycle if switch = 1. if the two adcs are used (one = 0) and an external adc clock (ext_clk = 1) is applied, the adc output is delayed with half adc clock cycle if switch = 1. if only one adc is used, the digital multiplexing is disabled by one = 1, but switch selects which adc output is on adc_d<9:0> (switch = 0: adc_1, switch = 1: adc_2). d. ext_clk if ext_clk = 0, the internal pixel clock (that drives the x-shift registers and output amplifier , that is, half the system clock) is used as input for the adc clock. if ext_clk = 1, an external clock must be applied to pin adc_clk_ext (pin 46). e. tristate if tristate = 1, the adc_d<9:0> outputs are in tri-state mode. f. delay_clk_adc the clock that finally acts on the adcs can be delayed to compensate for any delay introduced in the path from the analog outputs to the input stage of the adcs. the same settings apply for the delay that can be given to the clock acting on the output amplifier (see table 15). the best setting also depends on the delay of the output amplifier clock and the load of the output amplifier . it must be used to optimize the sampling moment of the adcs with respect to the analog pixel input signals. setting ?000? is used as a baseline. g. gamma if gamma is set to 0, the adc input to output conversion is linear, otherwise the conversion follows a ?gamma? law (more contrast in dark parts of the window, lower contrast in the bright parts). h. bitinvert if bitinvert = 0, 0000000000 is the conversion of the lowest possible input voltage, otherwise the bits are inverted.
NOII4SM6600A http://onsemi.com 23 timing diagrams sequencer control signals there are 3 control signals that operate the image sensor: ? sys_clock ? y_clock ? y_start these control signals must be generated by the external system with the following time constraints to sys_clock (rising edge = active edge): ? tsetup >7.5 ns ? thold > 7.5 ns it is important that these signals are free of any glitches. figure 17. relative timing of the three control signals basic frame and line timing the basic frame and line timing of the ibis4-6600 sensor is shown in figure 18. the pulse width of y_clock must be a minimum of one clock cycle and three clock cycles for y_st art. as long as y_clock is applied, the sequencer stays in a suspended state. t1 row blanking time: during this period, the x-sequencer generates the control signals to sample the pixel signal and pixel res et levels, and start the readout of one line. it depends on the granularity of the x-sequencer clock (see table 13 on page 20). t2 pixels counted by pixel counter until the value of nrof_pixels register is reached. pixel_valid goes high when the internal x _sync signal is generated. in other words, when the readout of the pixels is started. pixel_valid goes low when the pixel counter rea ches the value loaded in the nrof_pixels register. eol goes high sys_clock cycle after the falling edge of pixel_valid. t3 eof goes high when the line counter reaches the value loaded in the nrof_lines register and the line is read (pixel_valid goes low). t4 the time delay between successive y_clock pulses needs to be equal to avoid any horizontal illumination (integration) discrepancies in the image. both eof and eol can be tied to y_start (eof) and y_clock (eol) if both signals are delayed with at least 2 sys_clock periods to let the sensor run automatically. it must however be noted that on power-on, the first y_start and y_clock must be generated by the external system. figure 18. basic frame and line timing
NOII4SM6600A http://onsemi.com 24 pixel output timing using two analog outputs figure 19. pixel output timing using two analog outputs the pixel signal at the out1 (out2) output becomes valid after four sys_clock cycles when the internal x_sync (equal to start of pixel_valid output) appears (see figure 19). the pixel_valid and eol/eof pulses can be delayed by the user through the delay register. t1: row blanking time (see table 13 on page 20) t2: 4 sys_clock cycles. multiplexing to one analog output the pixel signal at the out1 output becomes valid after five sys_clock cycles when the internal x_sync (equal to start of pixel_valid output) appears (see figure 20). the pixel_valid and eol/eof pulses can be delayed by the user through the delay register. t1: row blanking time t2: 5 sys_clock cycles. figure 20. pixel output timing multiplexing to one analog output
NOII4SM6600A http://onsemi.com 25 adc timing two analog outputs figure 21 shows the timing of the adc using two analog outputs. internally, the adcs sample on the falling edge of the adc_clock (in case of internal clock, the clock is half the sys_clock). t1: each adc has a pipeline delay of 2 adc_clock cycles. this results in a total pipeline delay of four pixels. figure 21. adc timing using two analog outputs one analog output figure 22 shows the timing of the adc using one analog output. internally, the adc samples on the falling edge of the adc_clock. t1: the adc has a pipeline delay of 2 adc_clock cycles. figure 22. adc timing using one analog output
NOII4SM6600A http://onsemi.com 26 package information pin list description the following table lists all the pins and their functions. there are a total of 68 pins. all pins with the same name can be connected together. table 16. pin list pin pin name pin type expected voltage [v] pin description 1 cmd_col_ctu input 0 biasing of columns (ctu). decouple with 100 nf to gnda. 2 cmd_col input 1.08 biasing of columns. connect to v dda with r = 10 k and decouple to gnda with c = 100 nf. 3 cmd_colamp input 0.66 biasing of column amplifiers. connect to v dda with r = 100 k and decouple to gnda with c = 100 nf. 4 cmd_colamp_ctu input 0.37 biasing of column amplifiers. connect to v dda with r = 10 m and decouple to gnda with c = 100 nf. 5 rcal_dac_dark input 1.27 at code 128 dac_dark reg biasing of dac for dark reference. can be used to set output range of dac. default: decouple to gnda with c = 100 nf 6 rcal_dac_out input 0 biasing of dac for output dark level. can be used to set out- put range of dac. default: connect to gnda 7 v dda power 2.5 v dd of analog part [2.5 v] 8 gnda power 0 gnd (&substrate) of analog part 9 v ddd power 2.5 v dd of digital part [2.5 v] 10 gndd power 0 gnd (&substrate) of digital part 11 cmd_out_1 input 0.78 biasing of first stage output amplifiers. connect to vddamp with r = 50 k and decouple to gndamp with c = 100 nf. 12 cmd_out_2 input 0.97 biasing of second stage output amplifiers. connect to vddamp with r = 25 k and decouple to gndamp with c = 100 nf. 13 cmd_out_3 input 0.67 biasing of third stage output amplifiers. connect to vddamp with r = 100 k and decouple to gndamp with c = 100 nf. 14 spi_clk input - clock of digital parameter upload. shifts on rising edge. 15 spi_data input - serial address and data input. 16-bit word. address first. msb first. 16 vddamp power 2.5 v dd of analog output [2.5 v] (can be connected to v dda ) 17 cmd_fs_adc input 0.73 biasing of first stage adc. connect to vdda_adc with r = 50 k and decouple to gnda_adc with c = 100 nf. 18 cmd_ss_adc input 0.73 biasing of second stage adc. connect to vdda_adc with r = 50 k and decouple to gnda_adc. 19 cmd_amp_adc input 0.59 biasing of input stage adc. connect to vdda_adc with r = 180 k and decouple to gnda_adc with c = 100 nf. 20 gndamp ground 0 gnd (&substrate) of analog output 21 out1 output black level: 1 at code 190 dac_raw register analog output 1 22 adc_in1 input see out1. analog input adc 1 23 vddamp power 2.5 v dd of analog output [2.5 v] (can be connected to v dda ) 24 out2 output black level: 1 at code 190 dac_raw register analog output 2 25 adc_in2 input see out2. analog input adc 2 26 v ddd power 2.5 v dd of digital part [2.5 v] 27 gndd power 0 gnd (&substrate) of digital part 28 gnda power 0 gnd (&substrate) of analog part
NOII4SM6600A http://onsemi.com 27 table 16. pin list pin pin description expected voltage [v] pin type pin name 29 v dda power 2.5 v dd of analog part [2.5 v] 30 reg_clock input - register clock. data on internal bus is copied to correspond- ing registers on rising edge. 31 sys_clock input - system clock defining the pixel rate (nominal 40 mhz, 50% 5% duty cycle) 32 sys_reset input - global system reset (active high) 33 y_clk input - line clock 34 y_start input - start frame readout 35 gndd_adc power 0 gnd (&substrate) of digital part adc 36 vddd_adc power 2.5 v dd of digital part [2.5 v] adc 37 gnda_adc power 0 gnd (&substrate) of analog part 38 vdda_adc power 2.5 v dd of analog part [2.5 v] 39 vhigh_adc input 1.5 adc high reference voltage (for example, connect to vdda_adc with r = 560 and decouple to gnda_adc with c = 100 nf) 40 vlow_adc input 0.42 adc low reference voltage (for example, connect to gnda_adc with r = 220 and decouple to gnda_adc with c = 100 nf) 41 gnda_adc power 0 gnd (&substrate) of analog part 42 vdda_adc power 2.5 v dd of analog part [2.5 v] 43 gndd_adc power 0 gnd (&substrate) of digital part adc 44 vddd_adc power 2.5 v dd of digital part [2.5 v] adc 45 vdd_reset_ds power 2.5 (for no dual slope) variable reset voltage (dual slope) 46 adc_clk_ext input - external adc clock 47 eol output - diagnostic end of line signal (produced by sequencer), can be used as y_clk 48 eof output - diagnostic end of frame signal (produced by sequencer), can be used as y_start 49 pix_valid output - diagnostic signal. high during pixel readout 50 temp output - temperature measurement. output voltage varies linearly with temperature. 51 adc_d<9> output - adc data output (msb) 52 vdd_pix power 2.5 v dd of pixel core [2.5 v] 53 gnd_ab power 0 anti-blooming ground. set to 1 v for improved anti-blooming behavior 54 adc_d<8> output - adc data output 55 adc_d<7> output - adc data output 56 adc_d<6> output - adc data output 57 adc_d<5> output - adc data output 58 adc_d<4> output - adc data output 59 adc_d<3> output - adc data output 60 vdd_reset power 2.5 reset voltage [2.5 v]. highest voltage to the chip. 3.3 v for extended dynamic range or ?hard reset?. 61 adc_d<2> output - adc data output 62 adc_d<1> output - adc data output 63 adc_d<0> output - adc data output (lsb)
NOII4SM6600A http://onsemi.com 28 table 16. pin list pin pin description expected voltage [v] pin type pin name 64 bs_reset input - boundary scan (allows debugging of internal nodes): reset. tie to gnd if not used. 65 bs_clock input - boundary scan (allows debugging of internal nodes): clock. tie to gnd if not used. 66 bs_din input - boundary scan (allows debugging of internal nodes): in. tie to gnd if not used. 67 bs_bus output - boundary scan (allows debugging of internal nodes): bus. leave floating if not used. 68 cmd_dec input 0.74 biasing of x and y decoder. connect to v ddd with r = 50 k and decouple to gndd with c = 100 nf. note on power on behavior at power on, the chip is in an undefined state. it is advised that the power on is accompanied by the assertion of the sys_clock and a sys_reset pulse that puts all internal registers in their default state (all bits are set to 0). the x-shift registers are in a defined state after the first x_sync, which occurs a few microseconds after the first y_start and y_clock pulse. before this x_sync, the chip may draw more current from the analog power supply v dda . it is therefore favorable to have separate analog and digital supplies. the current spike (if there are any) may also be avoided by a slower ramp up of the analog power supply or by disconnecting the resistor on pin 3 (cmd_colamp) at startup.
NOII4SM6600A http://onsemi.com 29 package outline drawing figure 23. 68 pin lcc packaging outline
NOII4SM6600A http://onsemi.com 30 mechanical specifications table 17. mechanical specifications parameters description min typ max units die (with pin 1 to the left center) die thickness 0.74 mm die size 9120.1 x 11960.1 m die center, x offset to the center of package (?50) 0 (+50) m die center, y offset to the center of the package (?50) 0 (+50) m die position, x tilt ? 1 0 1 deg die position, y tilt ? 1 0 1 deg die placement accuracy in package (?50) (+50) m die rotation accuracy ?1 1 deg optical center referenced from package center (x ? dir) (?50) ? 155.58 (+50) m optical center referenced from package center (y ? dir) (?50) 446.95 (+50) m pixel (0,0) referenced from package center (x ? dir) (?50) ? 4023 (+50) m pixel (0,0) referenced from package center (y ? dir) (?50) ? 4806 (+50) m distance from pcb plane to top of the die surface 1.562 mm distance from the top of the die surface to the top of the glass lid 2.048 mm glass lid dimensions 19.5 x 17.5 mm thickness 1 mm spectral range for window 400 1000 nm transmission of the glass lid 92 % mechanical shock jesd22-b104c; condition g 200 g vibration jesd22-b103b; condition 1 20 2000 hz mounting profile lead ? free profile for lcc package if no socket is used
NOII4SM6600A http://onsemi.com 31 glass lid the ibis4-6600 image sensor uses a glass lid without any coatings. figure 24 shows the transmission characteristics of the glass lid. as shown in figure 24, no infrared attenuating filter glass is used. (source: http://www.pgo ? online.com). figure 24. transmission characteristics of the glass lid handling precautions for proper handling and storage conditions, refer to the on semiconductor application note an52561. limited warranty on semiconductor?s image sensor business unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to seller?s published specifications and will be free from defects in material and workmanship for two (2) years following the date of shipment. if a defect were to manifest itself within 2 (two) year period from the sale date, on semiconductor will either replace the product or give credit for the product. return material authorization (rma) on semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean-room-approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. acceptance criteria specification the product acceptance criteria is available on request. this document contains the criteria to which the ibis4-6600 is tested before being shipped. ordering code definition o = opto n = on semiconductor ibis4 m=mono q= lcc package commercial temperature range 6600 mq s = standard process 6.6 mp resolution additional functionality d= 263 glass i i = image sensors dc n o i4 s a ?
NOII4SM6600A http://onsemi.com 32 acronyms acronym description adc analog-to-digital converter afe analog front end bl black pixel data cdm charged device model cds correlated double sampling cmos complementary metal oxide semiconductor crc cyclic redundancy check dac digital-to-analog converter ddr double data rate dft design for test dnl differential nonlinearity ds double sampling dsnu dark signal non-uniformity eia electronic industries alliance esd electrostatic discharge fe frame end ff fill factor fot frame overhead time fpga field programmable gate array fpn fixed pattern noise fps frames per second fs frame start hbm human body model img regular pixel data inl integral nonlinearity acronym description ip intellectual property le line end ls line start lsb least significant bit lvds low-voltage differential signaling mbs mixed boundary scan msb most significant bit pga programmable gain amplifier pls parasitic light sensitivity prbs pseudo-random binary sequence prnu pixel random non-uniformity qe quantum efficiency rgb red green blue rma return material authorization rms root mean square roi region of interest rot row overhead time s/h sample and hold snr signal-to-noise ratio spi serial peripheral interface tbd to be determined tia telecommunications industry association t j junction temperature tr training pattern % rh percent relative humidity
NOII4SM6600A http://onsemi.com 33 glossary conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. conversion gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. cds correlated double sampling. this is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. dnl differential nonlinearity (for adcs) dsnu dark signal non-uniformity. this parameter characterizes the degree of non-uniformity in dark leakage cur- rents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. inl integral nonlinearity (for adcs) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixe l array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response non-uniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and converting them into electrons. it is photon wavelength and pixel color dependent. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. ?soft? reset occurs when the reset transistor is operated below the threshold. ?hard? reset occurs when the reset transistor is operated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodiode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wavelength. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux is equal to 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels.
NOII4SM6600A http://onsemi.com 34 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NOII4SM6600A/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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